Why a register, cache, Apple unified memory, NVIDIA HBM, Google TPU, Groq LPU, and Cerebras wafer-scale engine are all answers to the same problem: how to keep arithmetic fed with data.
Processors transform data. Memory stores data. In modern systems, the time and energy spent moving a value can exceed the cost of the arithmetic performed on it.
How long until the first requested byte arrives. Low latency matters for dependent, sequential work.
How many bytes arrive per second. High bandwidth matters when thousands of units need data continuously.
How much can be stored. More capacity is useful, but it is not automatically faster or closer.
Click each level. The approximate rankings are conceptual; exact latency and capacity depend on the processor and generation.
Registers hold operands being used now and are named or allocated by the instruction set and compiler. A cache automatically keeps copies of data from lower levels.
L1, L2, and L3 are normally built from SRAM. SRAM is a memory technology; “cache” is a role and management policy.
HBM dies are stacked and placed beside the accelerator on an advanced package. They are not part of the GPU logic die, but the path is short and extremely wide.
Apple unified memory is package-mounted LPDDR shared coherently by CPU, GPU, and accelerators. It reduces copies; it does not turn DRAM into SRAM.
Compute and memory were separate packages. As processors accelerated, waiting for DRAM became increasingly painful.
Small caches exploit locality and hide much of DRAM latency. Multiple cache levels emerge as one level cannot optimize size and speed simultaneously.
Thousands of parallel threads and vector units increase throughput—but only when memory systems keep them supplied.
CPU, GPU, media, and neural engines share package memory and a coherent address space, reducing copying and improving efficiency.
Advanced packages place dense DRAM or stacked SRAM near compute and connect smaller specialized dies with high-speed links.
A distributed sea of compute and SRAM avoids many chip boundaries. Defect tolerance, cooling, power delivery, and compiler mapping make the approach possible.
Research systems perform selected operations beside or within memory arrays, attempting to reduce movement further.
Select an architecture to see where compute, fast local storage, and bulk memory live.
A model's raw weight size is parameter count multiplied by bits per parameter. Real deployments also need KV cache, activations, workspace, and runtime overhead.
70B parameters
140 GB
Raw weights only; excludes runtime overhead.
Tensor, pipeline, or expert parallelism divides work and weights among accelerators. Communication becomes part of the critical path.
Fewer bits per parameter reduce capacity and bandwidth demand, sometimes with a quality or engineering tradeoff.
Weights can live in CPU memory, external parameter memory, or storage and move into fast memory as required. The risk is starving compute.
Only some weights or experts activate for a token. Hardware and software must avoid moving inactive data.
A one-trillion-parameter model at 16 bits per parameter occupies about 2 TB before KV cache, activations, workspace, and runtime overhead.
This is a simplified ceiling, not a token-per-second benchmark. It ignores communication, batching, model fit, kernel efficiency, sparsity, and streaming. In particular, a dense 1T FP16 model does not fit in 44 GB of on-wafer SRAM.
When a model is too large for one accelerator, its weights normally stay in fixed shards. The chips move activations and partial results—not the whole model—while every generated token makes another pass through the active weights.
With tensor parallelism, each GPU computes a slice of the same layer, then an all-gather, reduce-scatter, or all-reduce combines the pieces. With pipeline parallelism, different GPUs own different groups of layers and the activation moves stage to stage. Real systems commonly combine both.
A dense 1T model is 2 TB at FP16, so an imaginary five-way split still needs about 400 GB of raw weights per GPU. Five 180 GB B200s provide only 900 GB total: not enough for FP16 or FP8, although a 500 GB INT4 checkpoint could fit before KV cache and runtime overhead.
Not for one ordinary autoregressive sequence. Token 101 depends on token 100, so all five shards cooperate on token 101, then all five cooperate again on token 102. Independent requests and sequences can be batched in parallel; speculative decoding can also propose several candidates and verify them together.
Process the prompt's many tokens largely in parallel. Matrix-matrix work is compute-heavy, so FLOPS matter.
Generate one next token per sequence. At small batch sizes, reading the weights repeatedly often makes memory bandwidth the limit.
They accelerate prompt prefill, training, large batches, long-context attention, and multi-token verification. Batching lets one weight read serve many sequences, raising arithmetic per byte until compute becomes the bottleneck. A GPU can therefore have modest tokens/s per user but enormous aggregate tokens/s.
In NVIDIA's published tests, one H200 running Llama 3.1 70B produced about 51 output tok/s without a draft model and 114–146 tok/s with speculative decoding. An eight-GPU H200 system reached 268 tok/s per user in a separate low-latency test. A B200 throughput test reported 11,253 output tok/s for 70B FP4—but that is aggregate serving throughput, not one reader's stream.
Model, precision, prompt/output length, batch, latency target, software, and quality constraints must match before comparing.
Cerebras maps compute and weight pieces across the SRAM distributed over each wafer. Its published inference design splits models larger than one wafer at layer boundaries: about 20B FP16 parameters fit on one CS-3 and 70B on as few as four. A simple capacity extrapolation puts a dense 1T FP16 model near 50 wafers before overhead, but Cerebras has not published a matched 1T serving topology or benchmark here.
The model pieces still stay mapped and each output token is still sequential. The advantage is locality: within a wafer, 44 GB of SRAM and 21 PB/s of on-wafer memory bandwidth avoid much of the fine-grained GPU-to-GPU traffic. Cerebras reported 2,100 tok/s per user for 70B and 969 tok/s for 405B in vendor benchmarks that also used software techniques such as speculative decoding.
Fast per-user inference shortens reasoning, code generation, research agents, tool loops, and multi-agent workflows that may consume thousands of hidden or intermediate tokens before showing an answer. Voice benefits mainly from low time-to-first-audio and interruption latency. Video generation uses different image or latent tokens, so text tok/s is not a direct video-speed metric.
Aggregate throughput is the economic prize: if a replica emits more useful tokens per second while meeting the same latency target, it can serve more simultaneous users, so fewer replicas—and fewer chips—are needed.
The per-replica throughput is deliberately an input: for a 1T model, it must come from a benchmark using your exact model, precision, sequence lengths, batching policy, and latency SLO.
At 1,000 requests/s and 200 output tokens/request, the fleet must sustain 200,000 output tok/s—or 260,000 with 30% headroom. At 4,000 tok/s per 16-chip replica, that is 65 replicas and 1,040 chips.
Voice caveat: one request per minute is usually too coarse for an active voice session. Plan voice by concurrent sessions, turns per minute, time to first audio, interruption behavior, and audio real-time factor—not request rate alone.
p50/p95/p99 time to first token, inter-token latency, time per output token, queue time, and end-to-end response time.
Requests or output tokens completed within the TTFT and inter-token latency SLO—not merely work the hardware eventually finishes.
Output tok/s per GPU, per rack, and per megawatt; memory-bandwidth utilization; compute utilization; KV-cache occupancy and hit rate.
The clean endpoint metric is fully loaded cost per million accepted input and output tokens at the target SLO. Include amortized servers, networking, power, cooling, software, operations, idle capacity, and redundancy.
That mixes a flow rate with a unit cost. Use tok/s per dollar of provisioned capacity for infrastructure productivity, then $/million delivered tokens for unit economics. Always hold model quality and availability constant.
Choose a dimension. Scores below are qualitative teaching aids, not purchase benchmarks. Real rankings change with model, precision, batch size, latency target, software version, and system scale.
| Architecture | Main memory arrangement | Representative capacity | Bandwidth | Bandwidth ÷ 2 TB* |
|---|---|---|---|---|
| Intel Xeon server | DDR5 system memory | 512 GB–2 TB+ per socket | 307–410 GB/s | ≈ 0.18 tok/s |
| Apple M4 Max | Unified package LPDDR5X | Up to 128 GB | 546 GB/s | ≈ 0.27 tok/s |
| NVIDIA B200 | On-package HBM3e | 180 GB | 8.0 TB/s | ≈ 4.00 tok/s |
| Google TPU Ironwood | On-package HBM | 192 GB | 7.37 TB/s | ≈ 3.69 tok/s |
| Groq LPU | On-chip SRAM-centric | Not exposed as an HBM-like pool | No single comparable figure | Not comparable |
| Cerebras WSE-3 | Distributed on-wafer SRAM | 44 GB on-wafer | 21 PB/s on-wafer | 10,500 arithmetic quotient* |
*These divisions are intuition pumps, not deployable token rates. The memory tiers are unlike, the full model does not fit on one device, and distributed communication, KV cache, batching, model architecture, and utilization all intervene. The Cerebras quotient is especially non-realizable on one WSE because 2 TB of weights cannot fit in 44 GB.
Time to first token, tokens per second, tail latency, training time to target quality, and sustained utilization.
Cost per million tokens, completed training run, watt, rack, operator, network, cooling, and idle hour.
Framework support, libraries, compilers, debugging, model availability, reliability, and developer familiarity.
A specialist can become valuable by winning a meaningful slice of latency-sensitive inference, sovereign AI, private clusters, training, or scientific computing. The likely future is heterogeneous rather than one universal processor.
Google develops TPUs. AWS develops Trainium and Inferentia. Microsoft develops Maia. They may still offer NVIDIA and specialist third-party accelerators when customers demand them.
Repeat customers, cloud distribution, recurring utilization, matched-quality benchmarks, model launch cadence, gross margin, customer concentration, and supply-chain capacity.
Niche, strong specialist, broad platform, or commercial failure. Chip specifications alone cannot select the outcome or justify a market capitalization.
FLOPS · HBM · SRAM · DRAM · KV cache · chiplet · wafer-scale.
Product specifications and availability evolve. Recheck current documentation before engineering, procurement, or investment decisions.